FIG. 1 shows a block diagram of a conventional input/output (I/O) driver circuit 10 as used within an integrated circuit. The I/O driver circuit 10 provides signal conditioning for input signals and output signals associated with a coupled I/O block 12 such as an input/output circuit node. The I/O driver circuit 10 includes a PMOS driver 20 and an NMOS driver 22 that function to pull up and pull down, respectively, on signal line 24 coupled to the I/O block 12. The PMOS and NMOS drivers 20 and 22 are enabled for operation in response to assertion of the enable signals PDE and NDE as is typical for I/O driver operation. The PMOS and NMOS drivers 20 and 22 are designed to provide the required drive strength at optimal operating conditions (e.g., when process is fast, supply voltage is at a maximum, and temperature is low). However, as the operating conditions move toward more difficult parameters (e.g., when process slows, supply voltage begins to droop, and temperature is higher), the PMOS and NMOS drivers 20 and 22 are not able to provide the required drive strength. To address this concern, the I/O driver circuit 10 further includes compensation drivers to provide additional drive strength. The compensation drivers include: a PMOS process and temperature (PT) coded compensation driver 30, an NMOS PT-coded compensation driver 32, a PMOS voltage (V) coded compensation driver 40 and an NMOS V-coded compensation driver 42.
The PMOS PT-coded compensation driver 30 is configured to provide a pull up drive strength that is controlled by a digital PT-PMOS compensation control signal 34. For example, the PMOS PT-coded compensation driver 30 may include a plurality of PMOS transistors connected in parallel that are each individually controllable in response to the bits of the digital PT-PMOS compensation control signal 34 (e.g., four transistors for a 4-bit binary code). The more of the included transistors that are enabled by the digital PT-PMOS compensation control signal, the greater the pull up drive strength compensation provided by the PMOS PT-coded compensation driver 30 and, consequently, the greater the pull up drive strength of the overall I/O drive circuit 10. Conversely, the fewer of these transistors that are enabled by the digital PT-PMOS compensation control signal 34, the lesser the pull up drive strength contribution of the PMOS PT-coded compensation driver 30, and the lesser the pull up drive strength of the overall I/O drive circuit 10.
The NMOS PT-coded compensation driver 32 is configured to provide a pull down drive strength that is controlled by a digital PT-NMOS compensation control signal 36. For example, the NMOS PT-coded compensation driver 32 may include a plurality of NMOS transistors connected in parallel that are each individually controllable in response to the bits of the digital PT-NMOS compensation control signal 36 (e.g., four transistors for a 4-bit binary code). The more of the included transistors that are enabled by the digital PT-NMOS compensation control signal, the greater the pull down drive strength compensation provided by the NMOS PT-coded compensation driver 32 and, consequently, the greater the pull down drive strength of the overall I/O drive circuit 10. Conversely, the fewer of these transistors that are enabled by the digital PT-NMOS compensation control signal 36, the lesser the pull down drive strength contribution of the NMOS PT-coded compensation driver 32, and the lesser the pull down drive strength of the overall I/O drive circuit 10.
The PMOS V-coded compensation driver 40 is configured to provide a pull up drive strength that is controlled by a digital V-PMOS compensation control signal 44. For example, the PMOS V-coded compensation driver 40 may include a plurality of PMOS transistors connected in parallel that are each individually controllable in response to the bits of the digital V-PMOS compensation control signal 44 (e.g., three transistors for a 3-bit binary code). The more of the included transistors that are enabled by the digital V-PMOS compensation control signal, the greater the pull up drive strength compensation provided by the PMOS V-coded compensation driver 40 and, consequently, the greater the pull up drive strength of the overall I/O drive circuit 10. Conversely, the fewer of these transistors that are enabled by the digital V-PMOS compensation control signal 44, the lesser the pull up drive strength contribution of the PMOS V-coded compensation driver 40, and the lesser the pull up drive strength of the overall I/O drive circuit 10.
The NMOS V-coded compensation driver 42 is configured to provide a pull down drive strength that is controlled by a digital V-NMOS compensation control signal 46. For example, the NMOS V-coded compensation driver 42 may include a plurality of NMOS transistors connected in parallel that are each individually controllable in response to the bits of the digital V-NMOS compensation control signal 46 (e.g., three transistors for a 3-bit binary code). The more of the included transistors that are enabled by the digital V-NMOS compensation control signal, the greater the pull down drive strength compensation provided by the NMOS V-coded compensation driver 42 and, consequently, the greater the pull down drive strength of the overall I/O drive circuit 10. Conversely, the fewer of these transistors that are enabled by the digital V-NMOS compensation control signal 46, the lesser the pull down drive strength contribution of the NMOS V-coded compensation driver 42, and the lesser the pull down drive strength of the overall I/O drive circuit 10.
FIG. 2 shows a block diagram of an integrated circuit die 50 which includes the I/O driver circuit 10 and coupled I/O block 12. The I/O driver circuit 10 and coupled I/O block 12 are generally located at a peripheral circuit region of the integrated circuit 50. A core circuit region 52 of the integrated circuit die 50 includes functional circuitry (for example, digital circuitry, memory circuitry, digital processing circuitry, analog processing circuitry, etc.). The core circuit region 52 may, for example, be surrounded on all sides (or substantially surrounded on plural sides) by the peripheral circuit region. A centralized (or global) operating condition compensation circuit 54 located within the core circuit region 52 includes a process and temperature (PT) variation sensing circuit 56. The PT variation sensing circuit 56 generates the digital PT-PMOS compensation control signal 34 and the digital PT-NMOS compensation control signal 36 whose signal code values are dependent on variables such as process variations in the circuitry and performance variables due to temperature fluctuations that are applicable over all or substantially all of the integrated circuit die. U.S. Pat. No. 8,981,817 (incorporated by reference) teaches an example implementation of the centralized operating condition compensation circuit 54 (referred to as a PT-cell).
While the PT variation sensing circuit 56 is typically implemented centrally with respect to the die 50, voltage compensation is instead implemented closer to the I/O driver 10 at the peripheral circuit region of the die and thus concerns local conditions (i.e., conditions locally applicable to the peripheral circuit region of the die). However, a centrally generated reference voltage (such as an analog bandgap voltage) 60 is generated by a bandgap voltage generator circuit 64 and distributed from the centralized operating condition compensation circuit 54 in the core circuit region of the die 50 to the peripheral circuit region of the die. A localized voltage (V) compensation circuit 62 associated with an I/O drive circuit 10 at the peripheral circuit region of the die 50 receives the reference voltage 60 and generates the digital V-PMOS compensation control signal 44 and digital V-NMOS compensation control signal 46 whose signal code values are dependent on local voltage conditions of the I/O drive circuit 10 at the peripheral circuit region. U.S. Pat. No. 8,981,817 (incorporated by reference) teaches an example implementation of the localized voltage compensation circuit 62 (referred to as a V-cell).